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"A 3.0 Gb/s Throughput Hardware-Efficient Decoder for Cyclically-Coupled ..."

Qing Lu et al. (2016)

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DOI: 10.1109/TCSI.2015.2510619

access: closed

type: Journal Article

metadata version: 2024-05-28

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Qing Lu, Jianfeng Fan, Chiu-Wing Sham, Wai Man Tam, Francis C. M. Lau:
A 3.0 Gb/s Throughput Hardware-Efficient Decoder for Cyclically-Coupled QC-LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(1): 134-145 (2016)

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