"A 5.4-Gb/s Clock and Data Recovery Circuit Using Seamless Loop Transition ..."

Won-Young Lee, Lee-Sup Kim (2012)

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DOI: 10.1109/TCSI.2012.2190678

access: closed

type: Journal Article

metadata version: 2020-05-22

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Won-Young Lee, Lee-Sup Kim:
A 5.4-Gb/s Clock and Data Recovery Circuit Using Seamless Loop Transition Scheme With Minimal Phase Noise Degradation. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(11): 2518-2528 (2012)

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