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"A 50.8-53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- mum CMOS."

Chihun Lee et al. (2008)

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DOI: 10.1109/TCSII.2007.914430

access: closed

type: Journal Article

metadata version: 2020-05-27

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Chihun Lee, Lan-Chou Cho, Jia-Hao Wu, Shen-Iuan Liu:
A 50.8-53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- mum CMOS. IEEE Trans. Circuits Syst. II Express Briefs 55-II(5): 404-408 (2008)

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