"Analysis of the PLL jitter due to power/ground and substrate noise."

Payam Heydari (2004)

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DOI: 10.1109/TCSI.2004.838240

access: closed

type: Journal Article

metadata version: 2020-05-22

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Payam Heydari:
Analysis of the PLL jitter due to power/ground and substrate noise. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(12): 2404-2416 (2004)

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