"Memory Efficient Decoder Architectures for Quasi-Cyclic LDPC Codes."

Yongmei Dai, Ning Chen, Zhiyuan Yan (2008)

> Home

Details and statistics

DOI: 10.1109/TCSI.2008.922024

access: closed

type: Journal Article

metadata version: 2023-11-15

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcas/DaiCY08
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcas/DaiCY08
Yongmei Dai, Ning Chen, Zhiyuan Yan:
Memory Efficient Decoder Architectures for Quasi-Cyclic LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(9): 2898-2911 (2008)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.