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"40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist."

Yi-Wei Chiu et al. (2014)

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DOI: 10.1109/TCSI.2014.2332267

access: closed

type: Journal Article

metadata version: 2020-05-22

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  - https://dblp.org/rec/journals/tcas/ChiuHTZCJC14
Yi-Wei Chiu, Yu-Hao Hu, Ming-Hsien Tu, Jun-Kai Zhao, Yuan-Hua Chu, Shyh-Jye Jou, Ching-Te Chuang:
40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(9): 2578-2585 (2014)

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