"A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay ..."

Dong-Jin Chang et al. (2018)

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DOI: 10.1109/TCSII.2017.2689029

access: closed

type: Journal Article

metadata version: 2020-05-27

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Dong-Jin Chang, Min-Jae Seo, Hyeok-Ki Hong, Seung-Tak Ryu:
A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration. IEEE Trans. Circuits Syst. II Express Briefs 65-II(3): 281-285 (2018)

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