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"Jitter Minimization in Digital PLLs with Mid-Rise TDCs."
Luca Avallone et al. (2020)
- Luca Avallone, Michael Peter Kennedy, Saleh Karman, Carlo Samori, Salvatore Levantino:
Jitter Minimization in Digital PLLs with Mid-Rise TDCs. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(3): 743-752 (2020)
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