"High-level delay test generation for modular circuits."

Joonhwan Yi, John P. Hayes (2006)

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DOI: 10.1109/TCAD.2005.853697

access: closed

type: Journal Article

metadata version: 2020-09-24

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Joonhwan Yi, John P. Hayes:
High-level delay test generation for modular circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 576-590 (2006)

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