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"SDPR: Improving Latency and Bandwidth in On-Chip Interconnect Through ..."

Yoon Seok Yang et al. (2018)

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DOI: 10.1109/TCAD.2016.2570428

access: closed

type: Journal Article

metadata version: 2020-12-29

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  - https://dblp.org/rec/journals/tcad/YangDCG18
Yoon Seok Yang, Hrishikesh Deshpande, Gwan Choi, Paul V. Gratz:
SDPR: Improving Latency and Bandwidth in On-Chip Interconnect Through Simultaneous Dual-Path Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(3): 545-558 (2018)

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