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"Fault secure datapath synthesis using hybrid time and hardware redundancy."

Kaijie Wu, Ramesh Karri (2004)

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DOI: 10.1109/TCAD.2004.835132

access: closed

type: Journal Article

metadata version: 2020-09-24

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Kaijie Wu, Ramesh Karri:
Fault secure datapath synthesis using hybrid time and hardware redundancy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(10): 1476-1485 (2004)

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