default search action
"An Efficient Timing Model for CMOS Combinational Logic Gates."
Chung-Yu Wu et al. (1985)
- Chung-Yu Wu, Jen-Sheng Hwang, Chin Chang, Ching-Chu Chang:
An Efficient Timing Model for CMOS Combinational Logic Gates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4(4): 636-650 (1985)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.