"A test evaluation technique for VLSI circuits using register-transfer ..."

Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul (2003)

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DOI: 10.1109/TCAD.2003.814958

access: closed

type: Journal Article

metadata version: 2021-10-14

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Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul:
A test evaluation technique for VLSI circuits using register-transfer level fault modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(8): 1104-1113 (2003)

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