"An efficient delay test generation system for combinational logic circuits."

Eun Sei Park, M. Ray Mercer (1992)

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DOI: 10.1109/43.144857

access: closed

type: Journal Article

metadata version: 2020-09-24

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Eun Sei Park, M. Ray Mercer:
An efficient delay test generation system for combinational logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(7): 926-938 (1992)

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