"Leveraging Gate-Level Properties to Identify Hardware Timing Channels."

Jason Oberg et al. (2014)

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DOI: 10.1109/TCAD.2014.2331332

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type: Journal Article

metadata version: 2022-04-09

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Jason Oberg, Sarah Meiklejohn, Timothy Sherwood, Ryan Kastner:
Leveraging Gate-Level Properties to Identify Hardware Timing Channels. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(9): 1288-1301 (2014)

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