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"TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, ..."

Zihao Liu et al. (2018)

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DOI: 10.1109/TCAD.2017.2783860

access: closed

type: Journal Article

metadata version: 2022-07-04

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  - https://dblp.org/rec/journals/tcad/LiuMLWWCLWPG18
Zihao Liu, Mengjie Mao, Tao Liu, Xue Wang, Wujie Wen, Yiran Chen, Hai Li, Danghui Wang, Yukui Pei, Ning Ge:
TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 1985-1998 (2018)

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