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"A timing analysis algorithm for circuits with level-sensitive latches."

Jin-Fuw Lee, Donald T. Tang, Chak-Kuen Wong (1996)

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DOI: 10.1109/43.506140

access: closed

type: Journal Article

metadata version: 2021-09-06

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  - journals/tcad/LeeTW96
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  - https://dblp.org/rec/journals/tcad/LeeTW96
Jin-Fuw Lee, Donald T. Tang, Chak-Kuen Wong:
A timing analysis algorithm for circuits with level-sensitive latches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(5): 535-543 (1996)

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