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"Simultaneous floor plan and buffer-block optimization."

Iris Hui-Ru Jiang et al. (2004)

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DOI: 10.1109/TCAD.2004.826582

access: closed

type: Journal Article

metadata version: 2020-09-24

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  - https://dblp.org/rec/journals/tcad/JiangCJC04
Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao:
Simultaneous floor plan and buffer-block optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5): 694-703 (2004)

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