"Testing for multiple faults in domino-CMOS logic circuits."

Niraj K. Jha (1988)

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DOI: 10.1109/43.3138

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type: Journal Article

metadata version: 2020-09-24

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Niraj K. Jha:
Testing for multiple faults in domino-CMOS logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1): 109-116 (1988)

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