"Latency-Guided On-Chip Bus-Network Design."

Milenko Drinic et al. (2006)

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DOI: 10.1109/TCAD.2006.882488

access: closed

type: Journal Article

metadata version: 2020-09-24

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Milenko Drinic, Darko Kirovski, Seapahn Megerian, Miodrag Potkonjak:
Latency-Guided On-Chip Bus-Network Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2663-2673 (2006)

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