"Transistor-level estimation of worst-case delays in MOS VLSI circuits."

Michel R. Dagenais, Serge Gaiotti, Nicholas C. Rumin (1992)

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DOI: 10.1109/43.124425

access: closed

type: Journal Article

metadata version: 2022-06-13

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Michel R. Dagenais, Serge Gaiotti, Nicholas C. Rumin:
Transistor-level estimation of worst-case delays in MOS VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(3): 384-395 (1992)

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