"Layer assignment for VLSI interconnect delay minimization."

Maciej J. Ciesielski (1989)

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DOI: 10.1109/43.31525

access: closed

type: Journal Article

metadata version: 2020-09-24

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Maciej J. Ciesielski:
Layer assignment for VLSI interconnect delay minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(6): 702-707 (1989)

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