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"Testability analysis and test-point insertion in RTL VHDL specifications ..."

Samir Boubezari et al. (1999)

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DOI: 10.1109/43.784124

access: closed

type: Journal Article

metadata version: 2020-09-24

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Samir Boubezari, Eduard Cerny, Bozena Kaminska, Benoit Nadeau-Dostie:
Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9): 1327-1340 (1999)

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