"Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence ..."

Sarvesh Bhardwaj, Sarma B. K. Vrudhula (2008)

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DOI: 10.1109/TCAD.2008.916341

access: closed

type: Journal Article

metadata version: 2020-09-24

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Sarvesh Bhardwaj, Sarma B. K. Vrudhula:
Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(3): 445-455 (2008)

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