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"A time-based model for investigating parallel logic-level simulation."

Mary L. Bailey (1992)

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DOI: 10.1109/43.144846

access: closed

type: Journal Article

metadata version: 2020-09-24

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  - journals/tcad/Bailey92a
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Mary L. Bailey:
A time-based model for investigating parallel logic-level simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(7): 816-824 (1992)

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