Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance ..."

Lomash Chandra Acharya et al. (2023)

> Home

Details and statistics

DOI: 10.1109/TCAD.2022.3231173

access: closed

type: Journal Article

metadata version: 2023-08-05

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcad/AcharyaSMSDSMRD23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcad/AcharyaSMSDSMRD23
Lomash Chandra Acharya, Arvind Kumar Sharma, Neeraj Mishra, Khoirom Johnson Singh, Mahipal Dargupally, Nayakanti Sai Shabarish, Ajoy Mandal, Venkatraman Ramakrishnan, Sudeb Dasgupta, Anand Bulusu:
Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(8): 2657-2663 (2023)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.