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"Majority Logic Formulations for Parallel Adder Designs at Reduced Delay ..."

Vikramkumar Pudi, K. Sridharan, Fabrizio Lombardi (2017)

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DOI: 10.1109/TC.2017.2696524

access: closed

type: Journal Article

metadata version: 2022-06-23

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  persistent URL:
  - https://dblp.org/rec/journals/tc/PudiSL17
Vikramkumar Pudi, K. Sridharan, Fabrizio Lombardi:
Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity. IEEE Trans. Computers 66(10): 1824-1830 (2017)

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