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"Augmenting Loop Tiling with Data Alignment for Improved Cache Performance."

Preeti Ranjan Panda et al. (1999)

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DOI: 10.1109/12.752655

access: closed

type: Journal Article

metadata version: 2024-03-22

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  dblp key:
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  persistent URL:
  - https://dblp.org/rec/journals/tc/PandaNDN99
Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau:
Augmenting Loop Tiling with Data Alignment for Improved Cache Performance. IEEE Trans. Computers 48(2): 142-149 (1999)

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