"An Experimental Delay Test Generator for LSI Logic."

Jean Davies Lesser, John J. Shedletsky (1980)

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DOI: 10.1109/TC.1980.1675555

access: closed

type: Journal Article

metadata version: 2017-05-20

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Jean Davies Lesser, John J. Shedletsky:
An Experimental Delay Test Generator for LSI Logic. IEEE Trans. Computers 29(3): 235-248 (1980)

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