"A Selective Trigger Scan Architecture for VLSI Testing."

Mohammad Hosseinabady et al. (2008)

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DOI: 10.1109/TC.2007.70806

access: closed

type: Journal Article

metadata version: 2024-02-05

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Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi:
A Selective Trigger Scan Architecture for VLSI Testing. IEEE Trans. Computers 57(3): 316-328 (2008)

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