


default search action
"Seesaw: A 4096-bit vector processor for accelerating Kyber based on RISC-V ..."
Xiaofeng Zou et al. (2025)
- Xiaofeng Zou
, Yuanxi Peng, Tuo Li, Lingjun Kong, Lu Zhang:
Seesaw: A 4096-bit vector processor for accelerating Kyber based on RISC-V ISA extensions. Parallel Comput. 123: 103121 (2025)

manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.