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"CMOS logic gate performance variability related to transistor network ..."

Digeorgia N. da Silva, André Inácio Reis, Renato P. Ribas (2009)

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DOI: 10.1016/J.MICROREL.2009.07.023

access: closed

type: Journal Article

metadata version: 2020-02-22

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Digeorgia N. da Silva, André Inácio Reis, Renato P. Ribas:
CMOS logic gate performance variability related to transistor network arrangements. Microelectron. Reliab. 49(9-11): 977-981 (2009)

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