"A 4-bit, 250-MIPS processor using Josephson technology."

Yuji Hatano et al. (1990)

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DOI: 10.1109/40.52946

access: closed

type: Journal Article

metadata version: 2017-05-20

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  - https://dblp.org/rec/journals/micro/HatanoYMYHK90
Yuji Hatano, Shinichiro Yano, Hiroyuki Mori, Hiroji Yamada, Mikio Hirano, Ushio Kawabe:
A 4-bit, 250-MIPS processor using Josephson technology. IEEE Micro 10(2): 40-55 (1990)

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