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"Leakage reduction in dual mode logic through gated leakage transistors."

Neetika Yadav, Neeta Pandey, Deva Nand (2021)

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DOI: 10.1016/J.MICPRO.2021.104269

access: closed

type: Journal Article

metadata version: 2021-06-25

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  - https://dblp.org/rec/journals/mam/YadavPN21
Neetika Yadav, Neeta Pandey, Deva Nand:
Leakage reduction in dual mode logic through gated leakage transistors. Microprocess. Microsystems 84: 104269 (2021)

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