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"A low-cost synthesizable RISC-V dual-issue processor core leveraging the ..."

Karyofyllis Patsidis et al. (2018)

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DOI: 10.1016/J.MICPRO.2018.05.007

access: closed

type: Journal Article

metadata version: 2024-02-05

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Karyofyllis Patsidis, Dimitris Konstantinou, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension. Microprocess. Microsystems 61: 1-10 (2018)

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