"Minimization of digital logic gates and ultra-low power AES encryption ..."

V. Nandan, R. Gowri Shankar Rao (2020)

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DOI: 10.1016/J.MICPRO.2020.103000

access: closed

type: Journal Article

metadata version: 2020-11-18

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V. Nandan, R. Gowri Shankar Rao:
Minimization of digital logic gates and ultra-low power AES encryption core in 180CMOS technology. Microprocess. Microsystems 74: 103000 (2020)

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