"Formal timing analysis of gate-level digital circuits using model checking."

Qurat-ul Ain, Osman Hasan (2024)

> Home

Details and statistics

DOI: 10.1016/J.MICPRO.2024.105083

access: closed

type: Journal Article

metadata version: 2024-08-22

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/mam/AinH24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/mam/AinH24
Qurat-ul Ain, Osman Hasan:
Formal timing analysis of gate-level digital circuits using model checking. Microprocess. Microsystems 109: 105083 (2024)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.