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"A BCH error correction scheme applied to FPGA with embedded memory."

Yang Liu et al. (2021)

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DOI: 10.1631/FITEE.2000323

access: closed

type: Journal Article

metadata version: 2023-02-02

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  dblp key:
  - journals/jzusc/LiuLWZFL21
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  - https://dblp.org/rec/journals/jzusc/LiuLWZFL21
Yang Liu, Jie Li, Han Wang, Debiao Zhang, Kaiqiang Feng, Jinqiang Li:
A BCH error correction scheme applied to FPGA with embedded memory. Frontiers Inf. Technol. Electron. Eng. 22(8): 1127-1139 (2021)

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