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"An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin."

Cangsang Zhao et al. (1999)

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DOI: 10.1109/4.799864

access: closed

type: Journal Article

metadata version: 2022-07-05

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  - https://dblp.org/rec/journals/jssc/ZhaoBDKLNNSV99
Cangsang Zhao, Uddalak Bhattacharya, Martin Denham, Jim Kolousek, Yi Lu, Yong-Gee Ng, Novat Nintunze, Kamal Sarkez, Hemmige D. Varadarajan:
An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin. IEEE J. Solid State Circuits 34(11): 1564-1570 (1999)

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