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"A 6-GHz 16-kB L1 cache in a 100-nm dual-VT technology using a ..."

Yibin Ye et al. (2003)

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DOI: 10.1109/JSSC.2003.810057

access: closed

type: Journal Article

metadata version: 2022-10-02

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Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Ali Farhang, Vivek De:
A 6-GHz 16-kB L1 cache in a 100-nm dual-V_T technology using a bitline leakage reduction (BLR) technique. IEEE J. Solid State Circuits 38(5): 839-842 (2003)

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