"A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit."

Rong-Jyi Yang et al. (2006)

Details and statistics

DOI: 10.1109/JSSC.2006.874328

access: closed

type: Journal Article

metadata version: 2021-10-15

a service of  Schloss Dagstuhl - Leibniz Center for Informatics