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"An all-digital PLL for frequency multiplication by 4 to 1022 with ..."

Takamoto Watanabe, Shigenori Yamauchi (2003)

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DOI: 10.1109/JSSC.2002.807405

access: closed

type: Journal Article

metadata version: 2022-04-20

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Takamoto Watanabe, Shigenori Yamauchi:
An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time. IEEE J. Solid State Circuits 38(2): 198-204 (2003)

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