"An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode."

Shigeyoshi Watanabe et al. (1989)

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DOI: 10.1109/4.32038

access: closed

type: Journal Article

metadata version: 2024-11-12

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Shigeyoshi Watanabe, Yukihito Oowaki, Yasuo Itoh, Koji Sakui, Kenji Numata, Tsuneaki Fuse, Takayuki Kobayashi, Kenji Tsuchida, Masahiko Chiba, Takahiko Hara, Masako Ohta, Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, Takeshi Hamamoto, Kazunori Ohuchi, Fujio Masuoka:
An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode. IEEE J. Solid State Circuits 24(3): 763-770 (1989)

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