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ORCID"7.5 Gb/s monolithically integrated clock recovery circuit using PLL and ..."
Zhi-Gong Wang et al. (1994)
- Zhi-Gong Wang, Manfred Berroth, Ulrich Nowotny, Peter Hofmann, Axel Hiilsmann, Klaus Köhler, Brian Raynor, Joachim Schneider:
7.5 Gb/s monolithically integrated clock recovery circuit using PLL and 0.3-μm gate length quantum well HEMT's. IEEE J. Solid State Circuits 29(8): 995-997 (1994)
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