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"Bipolar transistor epilayer design using the MAIDS mixed-level simulator."

Leo C. N. de Vreede et al. (1999)

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DOI: 10.1109/4.782094

access: closed

type: Journal Article

metadata version: 2022-07-05

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  dblp key:
  - journals/jssc/VreedeGWNJLST99
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  persistent URL:
  - https://dblp.org/rec/journals/jssc/VreedeGWNJLST99
Leo C. N. de Vreede, Henk C. de Graaff, Joost A. Willemen, Wibo D. van Noort, Rik Jos, Lawrence E. Larson, Jan W. Slotboom, Joseph L. Tauritz:
Bipolar transistor epilayer design using the MAIDS mixed-level simulator. IEEE J. Solid State Circuits 34(9): 1331-1338 (1999)

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