"A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for ..."

Jeffrey Tyhach et al. (2005)

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DOI: 10.1109/JSSC.2005.852156

access: closed

type: Journal Article

metadata version: 2022-03-02

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Jeffrey Tyhach, Bonnie Wang, Chiakang Sung, Joseph Huang, Khai Nguyen, Xiaobao Wang, Yan Chong, Philip Pan, Henry Kim, Gopinath Rangan, Tzung-Chin Chang, Johnson Tan:
A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interface. IEEE J. Solid State Circuits 40(9): 1829-1838 (2005)

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