"Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS ..."

Cheng-Hsueh Tsai et al. (2020)

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DOI: 10.1109/JSSC.2020.2993717

access: closed

type: Journal Article

metadata version: 2020-08-30

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Cheng-Hsueh Tsai, Zhiwei Zong, Federico Pepe, Giovanni Mangraviti, Jan Craninckx, Piet Wambacq:
Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication. IEEE J. Solid State Circuits 55(7): 1854-1863 (2020)

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