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ORCID"A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop ..."
Satoru Tanoi et al. (1996)
- Satoru Tanoi, Tetsuya Tanabe, Kazuhiko Takahashi, Sanpei Miyamoto, Masaru Uesugi:
A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture. IEEE J. Solid State Circuits 31(4): 487-493 (1996)
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