"A 32-bank 256-Mb DRAM with cache and TAG."

Satoru Tanoi et al. (1994)

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DOI: 10.1109/4.328632

access: closed

type: Journal Article

metadata version: 2023-05-03

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Satoru Tanoi, Yasuhiro Tanaka, Tetsuya Tanabe, Akio Eta, Toshio Inada, Ryoji Hamazaki, Yoshio Ohtsuki, Masaru Uesugi:
A 32-bank 256-Mb DRAM with cache and TAG. IEEE J. Solid State Circuits 29(11): 1330-1335 (1994)

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