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"250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture."
Yasuhiro Takai et al. (1994)
- Yasuhiro Takai, Mamoru Nagase, Mamoru Kitamura, Yasuji Koshikawa, Naoyuki Yoshida, Yasuaki Kobayashi, Takashi Obara, Yukio Fukuzo, Hiroshi Watanabe:
250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture. IEEE J. Solid State Circuits 29(4): 426-431 (1994)
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